The transfer of data between devices at high speeds may be affected by noise generated both external and internal to the data transfer system. The transfer and reception of data are affected by noise that causes jitter and skewing of clocks and data signals. High speed buses, such as a serial advanced technology attachment (SATA) bus, designed for data transfers between a processor system and a hard disk drive, may operate at three gigabits per second with increased data rates beyond that already planned. At these high data rates, the generation of electromagnetic interference may be significant and steps are typically taken to reduce the radiated affect of the high speed signals. These steps include shielding and the use of spread spectrum techniques, for example.
A high speed serial interface with fixed rate clocking will generate electromagnetic energy that may interfere with nearby equipment. With fixed rate clocking, the radiated energy will be concentrated at the frequency of the clock and also at harmonic frequencies of the clock. The radiated energy can be reduced by varying the frequency of the clock within a specified range, including the desired frequency. This approach of varying the clock frequency is referred to as spread spectrum clocking and is one of the techniques used for SATA data transfers.
A conventional analog technique for generating offset frequencies that are offset from a reference frequency uses a phase detector coupled to a charge pump and filter to control a voltage controlled oscillator (VCO). The VCO generates a signal at a frequency based on a difference in phase of the reference signal frequency compared to a feedback VCO output signal frequency. By providing a time varying current component to the charge pump and filter output, the frequency generated by the VCO will vary accordingly. However, providing the time varying current component according to spread spectrum requirements may be difficult and costly to implement.
Another technique for generating offset frequencies is described in U.S. Pat. No. 6,919,744 (Paist) assigned to the assignee of the present invention. The frequency spreading of the phase locked loop (PLL) output signal frequency is controlled by periodically changing divisor values used in a fractional divider that is placed in the feedback path of the PLL. The divisor values are generated according to a desired spread spectrum profile and the fractional divider divides the PLL output signal, generated from an internal VCO, by the divisor values. The output of the fractional divider is compared to a reference signal in a phase detector of the PLL such that the VCO output frequency follows the desired spread spectrum profile.